1. Field of the Invention
The present invention relates to a NAND flash memory array and a fabricating method of the same, and more particularly to a NAND flash memory array having vertical channels and gate structures on sidewalls, wherein memory cells are formed in series on sidewalls of silicon pillars and a fabricating method of the same.
2. Description of the Related Art
These days, flash memories as non-volatile memories have been becoming popular. A conventional flash memory is classified as code flash and data flash, according to its application. In a code flash memory, a NOR type structure flash memory having a short random access time is used. A data flash memory uses a NAND type structure flash memory, which has a short writing time and a high integrity.
Particularly, NAND type flash memories, which have a high integrity because it is unnecessary to form contacts of source and drain on each cells, have been used mainly as large capacity storages in portable disks, digital cameras, video recorders, audio recorders and so on. As times have gone by, demands for NAND type flash memories have been increased.
Therefore, a reduction in cell size and electrical power consumption and a high speed operation have been needed to meet an increase in consumption for NAND flash memories.
Up to now, attempts to promote the degree of integrity of NAND flash memory arrays have been focused mainly on the reduction in cell size, based on planar structure. As a result from such attempts having problems with cell operation, there have been some limitations in improving integrity degree.
Therefore, manufacturers pass over memory arrays having conventional planar structures like FIG. 1, and try rather to develop memory arrays having three-dimensional structures, which embody memory cells by forming trenches on a silicon substrate and using sidewalls of the trenches.
The memory arrays having three-dimensional structures, as shown in FIG. 2, embody word lines on sidewalls as if one crushed the memory array having conventional planar structures into folded array. As a result, as you can see in FIG. 3, the area of one memory cell in a conventional planar structure is 2F×2F=4F2. However, in a three-dimensional structure like FIG. 4, the area is 2F×1F=2F2 only. The three-dimensional structure enables to reduce required areas of total array to a great amount and produce high integrity.
The representative prior art using the three-dimensional structure was described in U.S. Pat. No. 6,878,991.
The prior patent disclosed a floating gate type EEPROM memory. Silicon fins 128 are formed first, as shown in FIG. 5 and a floating gate 122 is formed on a tunnel insulator 120. A source/drain region 126 is formed by ion injection. Reference number 130 means trenches formed between silicon fins 128.
As shown in FIG. 6, one removes silicon fins 128 and poly-silicon, which is floating gates 122 in the direction of bit lines, fills oxide 132 into the area where the silicon fin removed and isolates an adjacent active region.
Then, as shown in FIG. 7, one deposits insulator 124, 142 and forms control gates 106 and select gates 144 respectively on the insulators.
However, the above prior patent has the following problems and it has difficulty in putting to practical use.
First, it is very difficult to isolate channels of cells in the prior invention. To isolate channels and floating gates, as shown in FIG. 6, one should remove silicon fins 128 and poly-silicon which is floating gates 122 by patterning in the direction of bit lines and to do so is not easy. Even if one removed silicon fins 128 and poly-silicon, it is still difficult to fill oxide 132 into the exact area only where the silicon fin removed.
Second, there is no solution for isolation between adjacent bit lines at source/drain regions formed on the bottom of trenches in the prior patent. In words, as shown in FIG. 5, because one forms silicon fins 128 and floating gates 122, injects ions directly and forms source/drain regions 126, there is a possibility that the bottom edges of trenches 130 along the direction of word lines will be coupled electrically to the adjacent bit lines. However, the prior invention did not provide any solution in the following process.
Third, in the prior invention, there must be a process for cutting floating gates, and it is a non-economic process. In the prior invention directed to floating gate types, one should cut floating gates connected in the direction of word lines as shown in FIG. 5, to the direction of each bit lines as shown in FIG. 6 in order to operate cells independently.